A clock divider circuit generates a clock of a desired frequency by dividing a frequency of a reference clock with a divider corresponding to a dividing ratio set in a register (refer to, for example, Japanese Laid-open Patent Publication Nos. 2003-248524, 2007-259125, 56-14758, 63-70321 and 2-202609). Power consumption of a system is minimized by switching the frequency of a clock by rewriting a register corresponding to an operating mode of the system. For example, when a plurality of circuit blocks within a system respectively use a plurality of clocks having different frequencies, the frequency of the clock supplied to each circuit block is changed by setting the register that determines the dividing ratio of the corresponding divider.
However, when switching frequencies of a plurality of clocks, since it is necessary to sequentially rewrite the corresponding registers, it takes time for rewriting of the clock frequencies to be completed. Since the circuit blocks do not operate until the clocks are switched, system performance ends up decreasing.